With the fast development of semiconductor manufacturing technology, integrated circuit manufacturing process has entered technology node of 22 nm or blow, the size of a semiconductor device and isolation structure for such semiconductor device has been reduced accordingly. After the 0.25 μm technology node, the isolation region between elements in an active region of a semiconductor device is typically formed by a shallow trench isolation (STI) process.
In the prior art, the process of forming a STI structure typically comprises the following steps:                First, as shown in FIG. 1a, forming a passivation layer 102 such as a silicon oxide plus silicon nitride composite layer on a surface of a substrate 100 and a patterned photoresist layer 104.        
Then, as shown in FIG. 1b, etching said passivation layer 102 by using the illustrated photoresist layer 104 as a mask to expose the substrate 100, and removing the photoresist layer.
After that, as shown in FIG. 1c, etching the exposed substrate to form a trench 106 by using the etched passivation layer 102 as a hard mask.
Thereafter, as shown in FIG. 1d, forming a lining oxide layer 108 at the sidewalls and bottom of a trench 90, then filling an insulating medium 110, such as silicon oxide, in the shallow trench, and planarizing the surface of the trench by a Chemical Mechanical Polishing (CMP) process.
After performing CMP, the hard mask is also removed, as shown in FIG. 1e. 
Then, when the feature size of a device is reduced to below 22 nm node, filling of STI will be a big problem, and the process tolerance of STI filling will also become narrower. It is still the same even if the most general high density plasma deposition (HDP) process and the more advanced high aspect ratio plasma deposition (HARP) process are used.
Besides, since the hard mask will be partly consumed in the processing of forming a trench, and the surface of the rest of the hard mask becomes rough, causing the height of the surface thereof becomes uneven. Particularly, the unevenness of the surface of the hard mask becomes even more obvious with the reducing of the feature size. From FIG. 1e it can be seen that a step height H, which is usually about 30 nm-50 nm, will be formed between the substrate region and the region filled with an insulating medium in the trench after the hard mask is removed. Unevenness of height of the hard mask surface will result in unevenness of step height in the same wafer surface. In the subsequent process steps, a gate dielectric layer and a polysilicon layer or a metal layer (for the current high-K metal gate structure) are formed on the surface of the active regions on the both sides of a trench. Since there is a step height in the formation of a STI structure, the profile of the polysilicon will become uneven, and there will be polysilicon residues when the polysilicon is etched thereafter. These polysilicon residues will cause a short circuit or leakage current path that harms the STI isolation function, which causes degradation of performance of the integrated circuit, resulting in reliability problem and device failure.
Therefore, a new STI isolation structure and a manufacturing method thereof is desired, by which the problem of filling a small-size trench without causing step height could be solved.
Besides, with the reducing of the size of an isolation structure, the isolation effect between devices is getting worse. Although in the case of the same transverse pitch P (the transverse width of an active region plus an isolation region) as shown in FIG. 1e, the isolation effect can be enhanced by increasing the transverse width D of the STI region, obviously, this will definitely reduce the effective area usable for the active region 114 of the device, resulting in deterioration of the device characteristics.
Therefore, a new STI isolation structure and a manufacturing method thereof are further desired, by which good characteristics of the device are kept while a good isolation effect is maintained.